This invention relates to a data control circuit and more particularly a data control circuit suitable for use with a shifter having a plurality of bit inputs.
Recently, in data processing, transfer of a desired number of bits of data is carried out frequently. In many data processors, data of, for example, a 16-bit external memory is transferred to desired bit positions of, for example, a 64-bit/word data internal memory incorporated in the processor chip and subsequently, the transferred 16-bit data is further desired to be exchanged between addresses of the 64-bit internal memory.
FIG. 1 shows one example of a prior art data control circuit having a function to select the number of bits to be transferred. The control circuit comprises a decoder 1 issuing outputs a-f, and a plurality of OR gate circuits 2 receiving one output, two outputs,, . . . six outputs of the decoder 1, the number of which outputs is incremented by one as the number of bits increases. The outputs of the OR gate circuits 2 are designated by A -F. In particular, the decoder 1 receives a signal indicative of a bit number of data to be transferred and activates only desired output signal lines which relate to the bit number to be transferred. Thus, in the illustrated example, only one output signal line is rendered high with the remaining output signal lines rendered low.
Suppose now that an output signal c among the output signals a-f of the decoder 1 becomes high level, only output signals D, E and F among the output signals A-F of the OR gate circuits 2 become high level, whereas the other output signals A, B and C become low level. The high level output signals D, E and F determine the number of bits to be transferred. In this manner, it is possible to detect only the number of bits to be transferred so as to transfer only the necessary bits.
Although this data control circuit is advantageous in that its output delay time is short, there is a defect in that the number of inputs for each OR gate circuit increases.
FIG. 2 shows another example of the prior art data control circuit
In the same manner as in FIG. 1, a decoder 1 determines the number of bits to be transferred and activates only desired output signal lines which relate to the bit number to be transferred, among output signal lines for output signals a through f. Each OR gate circuit 3 has two inputs, one input being connected to receive one of the output signals of the decoder 1 while the other input is supplied with the output signal of the OR gate circuit of the preceding stage. The output signals of the OR gate circuits 3 are designated by A to F. Suppose now that when the output signal c of the decoder 1 becomes high level, output signals D, E and F among the output signals A to F of the OR gate circuits 3 become high level, whereas output signals A, B and C become low level. Then, the output signals D, E and F at the high level determine the number of bits to be transferred.
Although the circuit shown in FIG. 2 is advantageous in that it is possible to reduce the number of inputs of the OR gate circuits 3 over that of the circuit shown in FIG. 1, there is a defect in that the output delay of each OR gate circuit is large since the FIG. 2 circuit comprises a serial connection in which the output of one OR gate circuit of a preceding stage is supplied to the input of the other OR gate circuit of a succeeding stage.
In a presently used processor having 64 or more bits, an increase in the number of inputs of each OR gate circuit or an increase in the output delay time is a detrimental defect that prevents practical use of such a processor.